Debugging Power-aware Designs

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Emerging power format standards allow one power definition to be used throughout design, verification and implementation. But they also increase complexity in verification and debugging. This article describes issues engineers face in debugging power-aware designs and the requirements for a solution.

For years, designers would implement power management directly in the gate-level netlist. But it is usually too late and too expensive to redesign issues found there. To verify power behaviour earlier, engineers began modelling power management in the RTL code. However, this is becoming impractical as power management is required on more modules, and the required power modes and transitions are growing quickly.

As a result, two standards have emerged for expression of power intent: the Common Power Format (CPF) and the Unified Power Format (UPF) both use TCL side files that allow engineers to describe the power Links:
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